LECC 2002, Colmar 8-13 SeptemberDavid Barney, CERN Design Verification – Digital Part Test I 2 C addressing on PACE-AM –If this doesn't work, stop testing Load/verify registers on Delta and PACE-AM –Can also read the default register values at power-on Put PACE into Run mode (set one bit in the PACE-AM control register) Set internal trigger to mode 0 (single ReSynch, single CalBurst) Examine basic digital signals via connectors on hybrids –ADC FIFO empty flag –Multiplexer signals –Data-valid signal –Loop signals (signify number of columns in the memory that are currently blocked) –Memory addresses of blocked columns (timing of trigger relative to a ReSynch can be used to determine a required column – and thus check that all columns are working)
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