Functional Clock Gating
{"Image DocumentName": "Functional Clock Gating", "Image ImageDescription": "P = \u00bd CswVdd DV f + IstVdd + IstaticVdd % of power consumption due to driving latches (Bose, Martinozi, Brooks %) Utilization of most latches is low (~10-35%) Gate off unused latches and associated logic: Unit level clock gating \u2013 turn off clocks to FPU, MMX, Shifter, L/S unit, \u2026 at clk buffer or splitter. Functional clock gating \u2013 turn off clocks to individual latch banks \u2013 forwarding latch, shift-amount register, overflow logic & latches, \u2026qualify (AND) clock to latch. Asynch is the most aggressive gating \u2013 but is it efficient?", "Image XResolution": "37", "Image YResolution": "37", "Image ResolutionUnit": "Pixels/Centimeter", "Image Software": "SlidePlayer", "Image YCbCrPositioning": "Centered"}