FPCA Delay Extraction Methodology: Each FPCA instance is replaced with F* instance (same I/0) Extract Delay Between F* instances Combined these Delay with Combinational Delay extracted for the FPCA Input Pins Output Pins SUM Define a pre-placed soft IP core : F* Same dimensions and I/O as FPCA Map onto Stratix II FPGA Extract critical path delay Replace all sum operations with F* Map compressor tree onto FPCA Configuration DFF values set to constant values ; not optimized Measure critical path delay For each compressor tree in the circuit Subtract delay of F* Add FPCA delay Methodology: F* FPCA 9/11
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