NIOS II Architecture Print sheet to list of architecture. All the ports on the right actually share one bus, the avalon archtecture.
{"Image DocumentName": "NIOS II ArchitecturePrint sheet to list of architecture. All the ports on the right actually share one bus, the avalon archtecture.", "Image ImageDescription": "-thirty two 32-bit general registers, six 32-bit control registers. -variable cache based on how much FPGA space you have. -ALU- 32bit two input to one input, does shifts, logic and arithmetic. Shifter is not separate like TigerSHARC.", "Image XResolution": "37", "Image YResolution": "37", "Image ResolutionUnit": "Pixels/Centimeter", "Image Software": "SlidePlayer", "Image YCbCrPositioning": "Centered"}