Sizing Logic Paths for Speed
{"Image DocumentName": "Sizing Logic Paths for Speed", "Image ImageDescription": "Frequently, input capacitance of a logic path is constrained. Logic also has to drive some capacitance. Example: ALU load in an Intel\u2019s microprocessor is 0.5pF. How do we size the ALU datapath to achieve maximum speed? We have already solved this for the inverter chain \u2013 can we generalize it for any type of logic?", "Image XResolution": "37", "Image YResolution": "37", "Image ResolutionUnit": "Pixels/Centimeter", "Image Software": "SlidePlayer", "Image YCbCrPositioning": "Centered"}