Technologie Mapping VHDL-Implementierung package tech_map is component inpad port (pad : in std_logic; q : out std_logic); end component;... end tech_
{"Image DocumentName": "Technologie Mapping VHDL-Implementierung", "Image ImageDescription": "package tech_map is. component inpad. port (pad : in std_logic; q : out std_logic); end component; ... end tech_map; entity inpad ... architecture rtl of inpad is. begin. ip0 : if TARGET_TECH = virtex generate. ipx : virtex_inpad port map (q => q, pad => pad); end generate; ip4 : if TARGET_TECH = atc18 generate. ipx : atc18_inpad port map (q => q, pad => pad); end rtl; type target_tech_type is. (gen, virtex, virtex2, apex, atc18, ...); constant TARGET_TECH : target_tech_type := apex;", "Image XResolution": "37", "Image YResolution": "37", "Image ResolutionUnit": "Pixels/Centimeter", "Image Software": "SlidePlayer", "Image YCbCrPositioning": "Centered"}