Power Aware Design Areas (I) Three main areas for power aware design System Design Development in CMOS technology -> improvements are slowing down Mul
{"Image DocumentName": "Power Aware Design Areas (I)", "Image ImageDescription": "Three main areas for power aware design. System Design. Development in CMOS technology -> improvements are slowing down. Multi-Chassis Systems: separate physical components clustered forming a single logical router. Aggregate power consumption increases -> heat spread over a large physical area -> existing cooling techniques used. Alternative Systems: optical switches. Terabits of bandwidth at much lower power dissipation. Protocols. Investigated in wireless networks -> Opportunities in wire-line networks. Basic notion: put components to sleep if low traffic load. Routing protocols: routes calculated with power consumption constraints.", "Image XResolution": "37", "Image YResolution": "37", "Image ResolutionUnit": "Pixels/Centimeter", "Image Software": "SlidePlayer", "Image YCbCrPositioning": "Centered"}