Block-Level 3D IC Design
{"Image DocumentName": "Block-Level 3D IC Design", "Image ImageDescription": "TSV Insertion and Floorplanning. TSV-whitespace. A 3D floorplanner is used to obtain 3D-IC layouts. TSVs are manually inserted into whitespace existing between blocks close to a pin of each 3D net. TSVs are irregularly placed. When TSVs are inserted, the current floorplan is perturbed by moving blocks to create or expand whitespace. Is expected to optimize the wirelength better than all other design styles since a 3D floorplanner is used.", "Image XResolution": "37", "Image YResolution": "37", "Image ResolutionUnit": "Pixels/Centimeter", "Image Software": "SlidePlayer", "Image YCbCrPositioning": "Centered"}