Experimental Methodology In-order 8-core 4GHz CMP processor –L1: private i-32KB/d-32KB –L2: private 2MB, 64B line –L3: DRAM off-chip, private 32MB, 256B line 4GB 2-bit MLC PCM main memory –One DIMM, single-rank, 8 banks –R/W queue 24 entries [HAY_MICRO'11] –Read first; schedule writes when NO read –Queue is full → write burst issuing all write until queue is empty –RESET: 500 cycles, 300μA, 480μW –SET: 1000 cycles, 150μA, 90μW –MLC non-deterministic write model [QURESHI_HPCA'10] Benchmarks –SPEC2006, BioBench, MiBench and STREAM 22
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