Register Organization Summary
{"Image DocumentName": "Register Organization Summary", "Image ImageDescription": "User. FIQ. IRQ. SVC. Undef. Abort. r8. r9. r10. r11. r12. r13 (sp) r14 (lr) r15 (pc) cpsr. r0. r1. r2. r3. r4. r5. r6. r7. User mode r0-r7, r15, and cpsr. User mode r0-r12, r15, and cpsr. User mode r0-r12, r15, and cpsr. User mode r0-r12, r15, and cpsr. User mode r0-r12, r15, and cpsr. Thumb state. Low registers. r8. r9. Thumb state. High registers. r10. r11. r12. This slide shows the registers visible in each mode - basically in a more static fashion than the previous animated slide that is more useful for reference. The main point to state here is the splitting of the registers in Thumb state into Low and High registers. ARM register banking is the minimum necessary for fast handling of overlapping exceptions of different types (e.g. ABORT during SWI during IRQ). For nested exceptions of the same type (e.g. re-entrant interrupts) some additional pushing of registers to the stack is required. r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) spsr. spsr. spsr. spsr. spsr. Note: System mode uses the User mode register set.", "Image XResolution": "37", "Image YResolution": "37", "Image ResolutionUnit": "Pixels/Centimeter", "Image Software": "SlidePlayer", "Image YCbCrPositioning": "Centered"}