© 2006 Altera Corporation 72 Pre-Compiled Design Units are Provided for RTL and Post Place and Route Simulation For OEM ModelSim only For MSE and MPE,
{"Image DocumentName": "ATOM Simulation Files (Verilog)", "Image ImageDescription": "Pre-Compiled Design Units are Provided for RTL and Post Place and Route Simulation. For OEM ModelSim only. For MSE and MPE, uncompiled source code is provided (with the exception of Stratix GX libraries which are always pre-compiled) Mapping Libraries. If you create a ModelSim project, all device families\u2019 libraries are pre-mapped for you. Otherwise, you must map each device family individually. eg. Stratix,Cyclone, etc. Device Libraries Would Be Manually Mapped. Map stratixii_ver to <ModelSim_install_dir>\\altera\\verilog\\stratixii. Map cyclone_ver to <ModelSim_install_dir>\\altera\\verilog\\cyclone.", "Image XResolution": "37", "Image YResolution": "37", "Image ResolutionUnit": "Pixels/Centimeter", "Image Software": "SlidePlayer", "Image YCbCrPositioning": "Centered"}