5 DAC 2014 - IP Track Submission Missing Synchronizer Detection in Power Reduction Some opportunities seem safe… …but may introduce a CDC problem  Any enable generated using meta-stable signal from the synchronizer crossing can lead to clock domain crossing issues in the finally obtained low-power design  Even though we get a low power optimized design using this flow, it may or may not be functionally correct if such type of issues are not caught before hand clk2 EN New enable by backward trace; no domain crossing clk1 clk2 EN Two flop synchronizer Metastable net should not be used for any purpose
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