ECE C03 Lecture 1319 Data Flow Modeling of Combinational Logic Consider a parity function of 8 inputs entity EVEN_PARITY is port (BVEC : in BIT_VECTOR(7 downto 0); PARITY: out BIT); end EVEN_PARITY; architecture DATA_FLOW of EVEN_PARITY is begin PARITY <= BVEC(0) xor BVEC(1) xor BVEC(2) xor BVEC(3) xor BVEC(4) xor BVEC(5) xor BVEC(6) xor BVEC(7) end DATA_FLOW;
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