©2004 Brooks/Cole Figure 17-19b: Structural Model of Sequential Machine 7architecture Structure of SM17_1 is 8signal A1,A2,A3,A5,A6,D3: bit:= 0 ; 9signal Q1,Q2,Q3: bit:= 0 ; 10signal Q1N,Q2N,Q3N, XN: bit:= 1 ; 11begin 12I1:Inverter port map (X,XN); 13G1:Nand3 port map (Q1,Q2,Q3,A1); 14G2:Nand3 port map (Q1,Q3N,XN,A2); 15G3:Nand3 port map (X,Q1N,Q2N,A3); 16G4:Nand3 port map (A1,A2,A3,D3); 17FF1: DFF port map (Q2N,CLK,Q1,Q1N); 18FF2: DFF port map (Q1,CLK,Q2,Q2N); 19FF3: DFF port map (D3,CLK,Q3,Q3N); 20G5:Nand2 port map (X,Q3,A5); 21G6:Nand2 port map (XN,Q3N,A6); 22G7:Nand2 port map (A5,A6,Z); 23end Structure;
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