Technical University of Lodz Department of Microelectronics and Computer Science Elements of high performance microprocessor architecture Cache organisation Fully Associative Cache 3The memory block can be placed in any cache line Tag Data Tag Data Tag Data Tag Data Tag Data 7Memory needed for tags increases with associativity 7Demand on board space - each cache entry has a comparator Choosing which block to replace 3LRU (least recently used) - requires additional bits for each cache line, updated during each access 3Random - candidates are selected randomly Address 7Slower access - complicated internal circuitry
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