General Remarks on TDC1190 TDC chip architecture  40 MHz input clock but 100 ps resolution can be achieved with PLL multiplication  Each channel can store up to 4 hit measurements before being written into a 256 words deep L1 buffer shared by 8 channels  In trigger matching mode a function will match hits with triggers based on trigger information stored in the Trigger Fifo (bunch id and event id) and a programmable matching window  The read-out FIFO is 256 words deep and enables data to be read out while others are being processed
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