Unsere erste Simulation besteht aus 4 Komponenten: ENTITY rsff IS PORT ( s,r : in std_logic; q,qn: out std_logic); END rsff; ENTITY test_rsff IS END test_rsff; ARCHITECTURE comb OF rsff IS BEGIN q <= not (r or qn); qn <= not (s or q) ; END comb; ARCHITECTURE struct OF test_rsff IS COMPONENT rsff PORT ( s,r : in std_logic; q,qn : out std_logic ); END COMPONENT; SIGNAL s,r,q,qn : std_logic ; BEGIN dut: rsff PORT MAP(s => s, r => r, q => q, qn => qn); s <= 1 , 0 after 10 ns, 1 after 100 ns, 0 after 130 ns, 1 after 300 ns, 0 after 350ns; r <= 1 , 0 after 10 ns, 1 after 200 ns, 0 after 230 ns; END struct;
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