EENG449b/Savvides Lec 17.16 3/29/05 Summary Reservations stations: implicit register renaming to larger set of registers + buffering source operands –Prevents registers as bottleneck –Avoids WAR, WAW hazards of Scoreboard –Allows loop unrolling in HW Not limited to basic blocks (integer units gets ahead, beyond branches) Today, helps cache misses as well –Don't stall for L1 Data cache miss (insufficient ILP for L2 miss ) Lasting Contributions –Dynamic scheduling –Register renaming –Load/store disambiguation
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