Parameterized Modules HDLs permit variable bit widths using parameterized modules  So far, all of our modules have had fixed-width inputs and outputs
{"Image DocumentName": "Parameterized Modules", "Image ImageDescription": "HDLs permit variable bit widths using parameterized modules. So far, all of our modules have had fixed-width inputs and outputs. Verilog allows a #(parameter \u2026)statement to define parameters before the inputs and outputs. module mux2. #(parameter width = 8) // name and default value. (input [width-1:0] d0, d1, input s, output [width-1:0] y); assign y = s ? d1 : d0; endmodule. Instance with 8-bit bus width (uses default): mux2 #(8) mux1(d0, d1, s, out); Instance with 12-bit bus width: mux2 #(12) lowmux(d0, d1, s, out);", "Image XResolution": "37", "Image YResolution": "37", "Image ResolutionUnit": "Pixels/Centimeter", "Image Software": "SlidePlayer", "Image YCbCrPositioning": "Centered"}