Frequency Synthesizer
{"Image DocumentName": "Frequency Synthesizer", "Image ImageDescription": "Automatic VCO band selection. Accumulation mode NMOS varactors. Off-chip 40 MHz XTAL and loop filter (~200 KHz) 3.5GHz. \u00b8 M. PFD. \u00b8 N. VH. decision. VL. Band Selection. The freq synthesizer is designed as an integer-N phase locked loop. The freq divider is implemented using a dual modulus 8/9 prescaler and a 13b pulse swallow counter. Freq synthesizer further contains a phase-freq-detector and a high performance charge pump. With a power supply voltage of 1.8 volts, the vco gain tends to be quite high in order to cover the required freq range. A high vco gain results in high sensitivity to the noise of vco tuning voltage, which increases the spur level and degrades phase noise. In this work, the required freq range is divided into nine bands, each about 60MHz wide with 30MHz overlap between adjacent bands. An automatic band selection scheme is implemented by connecting unit caps to the VCO core while monitoring the Varactor tuning voltage. Therefore achieve sufficient freq tuning range while maintaining a moderate VCO gain. Within each band, continuous freq tuning is achieved by using accumulation mode NMOS varactors. Using a ref clock at 40MHz, off-chip loop filter with bandwidth of roughly 200KHz is found to be optimal for phase noise performance. XTAL. timer. 3/18/2004.", "Image XResolution": "37", "Image YResolution": "37", "Image ResolutionUnit": "Pixels/Centimeter", "Image Software": "SlidePlayer", "Image YCbCrPositioning": "Centered"}