Proper Decoupling Design. Prevent signal integrity problems by understanding how to properly decouple power and grounds on your chip.
{"Image DocumentName": "Proper DecouplingDesign. Prevent signal integrity problems by understanding how to properly decouple power and grounds on your chip.", "Image ImageDescription": "Bulk vs filter capacitance. Electrolytic Bulk Capacitance. C = I / (dV/dt), size in uF depends on max transients. For example: I peak = 3A, Vnom = 3.3V, 10% V tolerance, 10usec delta time. C = 3A (10us/(3.3V 0.10) = 90.9uF => use 100uF Bulk cap  Ceramic High Frequency Capacitance. Typical values are 0.01uF, 0.1uF to 1uF depending on filtering frequency needed.  note: Devices are required to limit inrush on hot attach by limiting load to 10uF in parallel with 44ohms.", "Image XResolution": "37", "Image YResolution": "37", "Image ResolutionUnit": "Pixels/Centimeter", "Image Software": "SlidePlayer", "Image YCbCrPositioning": "Centered"}